1. Field of the Invention
The present invention relates to a power supply control circuit, and more particularly, to a power supply control circuit including an overvoltage protection circuit for protecting from an overvoltage an output transistor for controlling power supply to a load.
2. Description of Related Art
Japanese Unexamined Patent Application Publication No. 2007-28747 (JP 2007-28747A) and its equivalent US Patent Application Publication No. 2007/0014064 A1 disclose an exemplary power supply control circuit including an overvoltage protection circuit for protecting a power semiconductor device. A structure of the power supply control circuit will be described with reference to FIG. 1.
A conventional power supply control circuit 100 includes a gate charge discharging circuit 108, a gate resistance 107, an output MOS transistor (power semiconductor device) 109, a clamp selection switch 110, a dynamic clamping circuit 111, and a load 112. Connection in the power supply control circuit 100 will be described in the following in detail.
The output MOS transistor 109 includes, for example, an N-channel metal-oxide semiconductor field-effect transistor (MOSFET). A first terminal (for example, a drain) of the output MOS transistor 109 is connected to a first power supply line 101a which is in turn connected to a first power supply terminal 101 (for example, at a battery power supply potential), while a second terminal (for example, a source) of the output MOS transistor 109 is connected to a second power supply line 102a via the load 112. The second power supply line 102a is connected to a second power supply terminal 102 (for example, at a ground potential). An output terminal 106 is connected to a node between the output MOS transistor 109 and the load 112. One end of the gate resistance 107 is connected to a control terminal (for example, a gate) of the output MOS transistor 109. A first control signal 104 is input to the other end of the gate resistance 107. Further, the gate charge discharging circuit 108 is connected between the other end of the gate resistance 107 and the output terminal 106. The gate charge discharging circuit 108 is, for example, one MOS transistor. A drain of the gate charge discharging circuit 108 is connected to the other end of the gate resistance 107 while a source of the gate charge discharging circuit 108 is connected to the output terminal 106. A second control signal 105 is input to a gate of the gate charge discharging circuit 108.
The clamp selection switch 110 and the dynamic clamping circuit 111 are connected in series between the gate of the output MOS transistor 109 and the first power supply line 101a. In the power supply control circuit 100, the clamp selection switch 110 is one N-channel MOS transistor, and the dynamic clamping circuit 111 is one zener diode.
A source of the clamp selection switch 110 is connected to the gate of the output MOS transistor 109, a drain of the clamp selection switch 110 is connected to an anode of the dynamic clamping circuit 111, and a control terminal (for example, a gate) of the clamp selection switch 110 is connected to a reference voltage (for example, the ground potential) 103. Further, in the prior art, a substrate bias terminal of the clamp selection switch 110 is connected to the output terminal 106. A cathode of the dynamic clamping circuit 111 is connected to the first power supply line 101a. 
The clamp selection switch 110 is a switch between a conductive state and a non-conductive state based on the result of a comparison between two voltages. For example, the clamp selection switch 110 is a switch which is in the conductive state when the reference voltage 103 and a gate voltage of the output MOS transistor 109 are compared and a difference between the two voltages is larger than a threshold voltage of the MOS transistor as the clamp selection switch 110.
The dynamic clamping circuit 111 is a circuit which, when a voltage difference between the anode and the cathode is larger than a breakdown voltage of the diode, controls the voltage difference between the anode and the cathode to a predetermined voltage (for example, a dynamic clamping voltage) or lower.
The load 112 includes an inductive element such as a solenoid and/or a wire harness connected to the output terminal 106.
Operation of the power supply control circuit 100 is now described in detail. Here, the power supply control circuit 100 has three modes: a conductive mode in which the output MOS transistor 109 is in the conductive state and the load 112 generates a voltage at the output terminal 106; a negative voltage surge mode in which, when the output MOS transistor 109 is turned off and is in the non-conductive state, a negative surge voltage is generated at the output terminal 106; and a dump surge mode in which a positive surge voltage named as a dump surge voltage is generated in the first power supply line 101a because a battery terminal is disconnected while an alternator generates electricity. It is to be noted that the energy of the positive surge voltage as a dump surge is relatively large, and thus, it is necessary to prevent the output transistor from being destroyed by the surge. In the following, operation of the power supply control circuit 100 will be described in the respective three modes.
First, in the conductive mode, when the first control signal 104 is at high level, the output MOS transistor 109 is in the conductive state. High level of the first control signal 104 is, for example, a voltage obtained by boosting the battery power supply voltage in order to make the output MOS transistor 109 in the conductive state with a low channel resistance. This generates a voltage at the load 112, and the voltage is output from the output terminal 106. In this case, the gate charge discharging circuit 108 is controlled by the second control signal 105 having the phase reversed to that of the first control signal 104. A low level of the second control signal 105 is, for example, the ground potential. When the second control signal 105 is at low level, the gate charge discharging circuit 108 is in the non-conductive state.
Here, in the conductive mode, because the gate voltage of the clamp selection switch 110 is the ground potential, the clamp selection switch 110 is, regardless of the value of the gate voltage of the output MOS transistor 109, in the non-conductive state. Therefore, the gate of the output MOS transistor 109 and the dynamic clamping circuit 111 are disconnected and current does not flow from the gate of the output MOS transistor 109 to the first power supply line 101a. In other words, the clamp selection switch 110 also has a function to prevent backflow of current from the gate of the output MOS transistor 109 to the first power supply line 101a. 
Next, operation in the negative voltage surge mode will be described. A negative surge voltage is generated when the output MOS transistor 109 is turned off and is in the non-conductive state. In this case, the first control signal 104 is at low level while the second control signal 105 is at high level. Here, low level of the first control signal 104 is, for example, the ground potential, and high level of the second control signal 105 is the battery power supply voltage.
When the second control signal 105 is at high level, the gate charge discharging circuit 108 is in the conductive state. Therefore, the gate charge of the output MOS transistor 109 is discharged via the gate resistance 107 and the gate charge discharging circuit 108. Here, the output MOS transistor 109 is made to be in the non-conductive state, and thus, an inductive element of the load 112 generates the negative surge voltage. Here, the clamp selection switch 110 is electrically connected to the output terminal 106 via the gate resistance 107 and the gate charge discharging circuit 108. Because the output MOS transistor 109 is in the non-conductive state, the inductive element of the load 112 generates the negative surge voltage as illustrated in FIG. 2.
Generation of the negative voltage drops the voltage at the output terminal 106. Here, the gate charge discharging circuit 108 is in the conductive state. Therefore, the voltage at the output terminal 106 and the gate voltage of the output MOS transistor 109 are substantially the same, and, according to the voltage drop of the output terminal 106, the gate voltage of the output MOS transistor 109 also drops. When the potential difference between the gate voltage of the clamp selection switch 110 and the gate voltage of the output MOS transistor 109 becomes larger than the threshold voltage of the clamp selection switch 110, the clamp selection switch 110 is made to be in the conductive state. When, after that, the gate voltage of the output MOS transistor 109 further drops and the potential difference across the dynamic clamping circuit 111 becomes equal to or larger than the breakdown voltage of the dynamic clamping circuit 111, a dynamic clamping voltage is generated across the dynamic clamping circuit 111. Further, the output MOS transistor 109 is made to be in the conductive state. This makes the voltage between the drain and the gate of the output MOS transistor 109 controlled by the dynamic clamping voltage. Further, the voltage between the drain and the source of the output MOS transistor 109 is controlled by a voltage value which is the sum of the dynamic clamping voltage and the threshold voltage of the output MOS transistor 109.
In this case, because the output MOS transistor 109 is in the conductive state, current determined by a resistive element of the load flows between the drain and the source of the output MOS transistor 109. In other words, power consumption of the output MOS transistor 109 is equal to the product of the dynamic clamping voltage and the current value determined by the resistive element of the load. The resistive element of the load is set such that thermal destruction of the output MOS transistor 109 by the power consumption does not occur. Further, current determined by dividing the threshold voltage of the output MOS transistor 109 by the resistance value of the gate resistance 107 flows through the dynamic clamping circuit 111. The current is, for example, approximately several tens of microamperes.
Next, operation in the dump surge mode will be described. A dump surge as illustrated in FIG. 3 is applied to the first power supply line 101a and the voltage at the first power supply line 101a is raised. In this case, the gate voltage of the clamp selection switch 110 is the ground potential, and the output terminal 106 is at a positive voltage, and thus, the clamp selection switch 110 is in the non-conductive state. In other words, the gate of the output MOS transistor 109 and the first power supply line 101a are disconnected. Therefore, the gate voltage of the output MOS transistor 109 is not affected by voltage fluctuations of the first power supply line 101a. More specifically, the output MOS transistor 109 is in the non-conductive state when the second control signal 105 is at high level.
In this way, the output MOS transistor 109 is in the non-conductive state and the voltage between the source and the drain is the dump surge voltage. Here, because the breakdown voltage between the drain and the gate and the breakdown voltage between the drain and the source of the output MOS transistor 109 are generally designed so as to be higher than the dump surge voltage, the output MOS transistor 109 is not destroyed by the dump surge.
As described above, in the conventional power supply control circuit 100, by making the clamp selection switch 110 in the conductive state according to change in the output terminal 106 in the negative voltage surge mode, the dynamic clamping circuit 111 is operated to protect the output MOS transistor 109 from the negative surge voltage. In the conductive mode and the dump surge mode, because the output terminal 106 does not generate a negative voltage, the clamp selection switch 110 is in the non-conductive state and the dynamic clamping circuit 111 is inoperative. In other words, the power supply control circuit 100 is a circuit which, when the voltage at the output terminal 106 is a negative voltage, protects the output MOS transistor 109 using the dynamic clamping circuit 111, and, in other modes, prevents destruction not by using the dynamic clamping circuit 111 but by the breakdown voltage of the output MOS transistor 109.
Such a power supply control circuit including an overvoltage protection circuit is extensively used as a power switch for automotive electrical components. Meanwhile, the present inventor seeks to further improve the reliability taking the usage environment into consideration, and seeks to protect the output transistor even from a surge which is higher than the dump surge voltage but has a smaller energy (hereinafter, referred to as positive spike surge voltage). Such a positive spike surge voltage has a voltage waveform as illustrated in FIG. 4.
The present inventor noticed that the power supply control circuit 100 illustrated in FIG. 1 is ineffective against such a positive spike surge voltage and the output MOS transistor 109 is broken down to be destroyed. Because the dynamic clamping circuit 111 is adapted to be inoperative in relation to the dump surge (see FIG. 3) generated at the first power supply terminal 101, when an overvoltage higher than the dump surge is applied as the positive spike surge voltage, if the voltage is equal to or higher than the breakdown voltage of the output MOS transistor 109, the output MOS transistor 109 is destroyed.